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JEDEC Announces LPDDR5 RAM For Mobile Computing Devices

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JEDEC Announces LPDDR5 RAM For Mobile Computing Devices

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JEDEC is a well known name in the microelectronics sector. JEDEC Solid State Technology Association announced the publication of the new JESD209 LPDDR5 RAM on February 21. LPDDR stands for Low Power Double Data Rate 5, implying that the RAM module is targeted towards mobile computing devices. LPDDR5 will run at 6400 MT/s I/O rate, which is almost 50% higher than the first iteration of the LPDDR4 mobile RAM. The increased transfer rate provided by LPDDR5 will notably give a boost to the efficiency and memory speed of the device. Devices that have low power consumption such as Notebooks, tablets and smartphones can especially benefit from the new module.

Furthermore, LPDDR5 has some new components that are specifically designed for mission-critical applications. The original LPDDR5 architecture has been redesigned and now runs on a whole new 16Banks programmable structure with an integrated multi-clocking architecture. Also, the LPDDR5 documentation is available for download here.

New Commands

Two revamped command-based operations have been introduced to the new RAM module. They aim towards the improvement of system power consumption while reducing data transmission at the same time. Named Data-copy and Write-X, the operations will keep a check on the overall power consumption of smartphones and laptops.

The Data-copy command will provide instructions to the LPDDR5 module to copy the data on a single I/O pin to the other I/O pins. This will ensure that data is not needlessly transmitted to the rest of the pins. On the other hand, the Write-X command will instruct the device to write all-ones or all-zeroes to a specific address, which will eliminate the need to transfer data from the chipset to the device itself.

Other Features

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Along with the announcement of the new module, LPDDR5 has included Link Error Correcting Code support for the SoC-DRAM interface. It helps boost higher data transfer rates between the components. Other features include Dynamic Frequency and Voltage Scaling for Core and I/O, selectable differential and single-ended CK, WCK, and RDQS, partial array self-refresh and auto-refresh, and low power read/write operation with Data-Copy and Write-X functions.

 

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Anubhav Sharma
Anubhav Sharma
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